1. Technical Field
The present invention relates to nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory device for supporting a high-speed search in cache memory.
2. Discussion of the Related Art
Recent rapid development of information processing devices such as computers etc. have led to the development of semiconductor memory devices with high speeds and large capacities.
In general, a semiconductor memory device is classified as either a volatile semiconductor memory device or a nonvolatile semiconductor memory device. Examples of volatile semiconductor memory devices include dynamic random access memory and static random access memory.
An example of nonvolatile semiconductor memory device is an EEPROM. Modern EEPROM may be high density and electrically erasable. Moreover, modern applications for EEPROM often involve use in compact portable electronics such as digital cameras and portable computers, where a large amount of data may need to be stored in a relatively small device. Accordingly, EEPROMS having small sizes and high densities are desirable.
Flash EEPROM is classified as NAND, NOR and AND types. NAND-type EEPROMS utilizing a flash erase function may be particularly suited for use as large capacity auxiliary memory owing to their relatively high density as compared to NOR or AND-type EEPROMS.
A configuration of general nonvolatile semiconductor memory device, and a sectional face of memory cells in a memory cell array are disclosed in, for example, U.S. Pat. No. 6,295,227 issued on Sep. 25, 2001, which is incorporated by reference.
As flash memory becomes more highly integrated and higher speed, flash memory may be applied as a cache memory. Flash memory may be used as a temporary storage space of a large capacity of data storage device such as HDD etc. In such devices, NAND flash memory cell array and an SRAM memory are configured within a single chip, for example, the OneNAND fabricated by Samsung Electronics.
FIG. 1 illustrates an address mapping correlation between a large capacity storage device and a flash memory according to a conventional art.
A hard disk drive (HDD) 10 is a large capacity storage device having a data storage capacity of, i.e., 80 GB to 160 GB, and a OneNAND 100 having a flash memory internal structure is used as a cache memory. Though not shown in FIG. 1, an external host, i.e., micro controller, memory controller, CPU etc., first accesses the OneNAND 100 that functions as a cache memory in reading data stored in the HDD 10. The OneNAND 100 has a logical address and a physical address. Thus, the host first applies a logical address (step S2) to the OneNAND 100 in a data read request (step S1) and then receives a physical address mapped with the logical address from the OneNAND 100, thereby reading data.
As a result, as shown in FIG. 1, when the flash memory 100 is used as a temporary storage space of the large capacity storage device 10 like in the application to hybrid HDD, the host should decide whether there is read data in flash memory 100 serving as the temporary storage device, in a read request operation. This decision can be obtained by searching for a map table with storage of logical address among data stored in the flash memory 100. Time taken in the map table search lowers a read performance in the application for hybrid HDD.
FIG. 2 illustrates increased map search time in a read time according to a conventional art. A reference character A1 indicates a time interval of table map search, and A2 indicates a time interval of data transmission. With a data capacity of 128 to 256 MB as illustrated in FIG. 1, a data transmission time is about 70 microseconds, while, a table map search time is about 80 microseconds. When representing an overall read operation of FIG. 2 as a data transmission rate, the data transmission rate becomes 26.7 MB/S. As shown in an arrow AR1, the table map search time A1 may be reduced to A10.